The register

Headline-level retellings collapsed the verified factorisation of the single RSA-129 challenge into the broader claim that RSA had been cracked.

The proposed TWINKLE optoelectronic siever was projected to increase factorable size by 100–200 bits and make 512-bit RSA very vulnerable.

A proposal and newspaper headline claimed a fast RSA decode by finding an exponent x with 2^x=1 mod N, based on small spreadsheet tests.

A circuit proposal claimed roughly 3.009 times as many decimal digits could be factored for the same construction-cost-times-latency budget.

A proposed device was projected to perform the NFS matrix step for RSA-1024 in one day for a few thousand US dollars under an optimistic matrix-size assumption.

The TWIRL VLSI design projected NFS sieving of 512-bit inputs in under ten minutes for about US$10,000 and 1,024-bit inputs in under one year for about US$10 million.

A deterministic digit-by-digit depth-first search was presented as a fast RSA-factoring algorithm whose runtime depends on decimal input length.

A forum post claimed that the general factoring problem was solved.

A secondary report presented the special-form factorisation of 2^1039−1 as meaning ordinary RSA-1024 was dead.

Work-in-progress slides proposed a deterministic general factoring algorithm of roughly exp(c√(log N log log N)) complexity, conditional on a missing step.

Reports described 256-bit demonstrations in about 50 seconds, projected 512 bits in about five hours, and promoted the reciprocal method as a practical threat to public-key cryptography.

The 2021 preprint projected factoring 400- and 800-bit integers with low-dimensional lattices and low operation counts, concluding that the method destroyed RSA.

Two preprints proposed polynomial-time RSA inversion or equivalent-key attacks when associated sequences have polynomially bounded linear complexity.

A viXra preprint and follow-up records claimed very short algorithms would factor RSA-2048 or RSA-617, with another result expressly approximate.

A preprint conjectured a classical subexponential factorisation method conditional on finding an elliptic curve and point with specified even-order properties.

A post gave an O((log n)^2) operation count for factoring on an idealised machine with constant-cost arithmetic on arbitrarily large integers.

A workshop talk claimed average-time polynomial SVP/CVP behaviour could yield polynomial-time integer factoring under geometric-series and short-vector assumptions.

A Bayesian-network and linear-programming construction was claimed to give deterministic polynomial-time factoring and to warrant re-evaluating factoring-based cryptography.

A preprint claimed deterministic polynomial-time factorisation by reducing the problem to two-dimensional convex integer minimisation.

A CVP chapter used heuristic prime-number-lattice behaviour as a route to polynomial-time factoring.

A Dagstuhl report claimed polynomial-time SVP/CVP for low-relative-density lattices under reasonable heuristics and applied it to factoring, with examples around 10^14.

A worked example for 187=11×17 was presented as logarithmic-time integer factorisation.

A classical tensor-network method reported finite-size numerical evidence of polynomial resource scaling, factoring RSA semiprimes to 100 bits and simulating encodings to 130 bits.

Arnold's Factorization Algorithm was described as polynomial-time with potential cryptographic relevance and illustrated on semiprimes up to 12 decimal digits.

A 2025 talk continued the prime-number-lattice polynomial-time programme and estimated an 800-bit input at lattice dimension 900.

A preprint abstract claimed an explicit deterministic and provably polynomial framework for factoring RSA-type semiprimes.

A follow-up manuscript presented an algebraic-analytic framework connecting deterministic polynomial-time semiprime factorisation with the Riemann hypothesis.

A preprint claimed O(log^2 n log log n) deterministic factoring of arbitrary RSA semiprimes by monotone binary search over rounded roots.

A seven-spin liquid-state NMR experiment implemented a compiled Shor instance for 15.

A one-way photonic architecture demonstrated a compiled Shor circuit for 15.

A four-qubit photonic circuit implemented a compiled Shor factorisation of 15.

A three-qubit NMR experiment encoded and recovered factors of 21 with an adiabatic method, while favourable runtime scaling was studied in simulation.

Four photonic qubits on an integrated silica-on-silicon chip ran a compiled Shor circuit for 15.

A four-qubit NMR system ran an instance-reduced adiabatic Hamiltonian whose ground state encoded 143=11×13.

A three-qubit superconducting processor ran a compiled Shor circuit for 15 and reported correct factors in 48% of repetitions.

A two-photon recycled-qubit circuit was presented as a compiled order-finding method to factor 21.

Simplified Shor circuits were proposed for selected products of Fermat primes, including 51 and 85.

A methodological construction showed that answer-dependent compiled Shor circuits can appear to factor arbitrarily large selected products in constant time with two coherent qubits.

Selected semiprimes including 3,599, 11,663 and 56,153 were reduced to the same four-variable Hamiltonian family used for 143, with a three-variable construction for 175.

An ion-trap experiment presented a scalable Kitaev-style Shor architecture and factored 15 with generalized modular multipliers.

A D-Wave 2X experiment reported selected biprime factorisations above 200,000 after Gröbner-basis preprocessing.

A three-qubit room-temperature NMR experiment reported factorisation of 291,311 after classical reduction to a three-variable Hamiltonian.

A hybrid IBM scheme reported factoring 4,088,459 and other selected integers with very small circuits.

A D-Wave 2000Q multiplication-table formulation was demonstrated on selected targets through 376,289 using up to 94 logical variables.

Compiled IBM circuits recovered expected periods for 15 and assigned the correct period for a selected 21 instance.

A compiled IBM Shor experiment attempted to factor 35 with base 4.

A fault-tolerant surface-code estimate projected factoring RSA-2048 in about eight hours with about 20 million noisy physical qubits.

A hybrid annealing formulation reported factoring 1,005,973 with 89 binary variables.

A four-photon cluster-state circuit using a semiconductor quantum-dot source factored 15.

An automated D-Wave 2000Q QUBO pipeline reported selected hardware factorisations through 103,459.

A hybrid adiabatic IBM experiment factored 35 after classical reduction of the biprime optimisation problem.

An optimised Ising formulation reported factoring integers through 1,028,171 with 88 logical variables.

QAOA-based variational factoring ran selected targets including 1,099,551,473,989 on a superconducting processor using three to five qubits.

A variational imaginary-time method reported hardware factorisations through 91 and a larger set in simulation.

A five-qubit compiled quantum-phase-estimation circuit on IBM processors completed factor extraction for 21.

A cat-code and multimode-memory architecture estimated RSA-2048 factoring with 13,436 processor qubits in 177 days.

A hybrid Schnorr-lattice/QAOA experiment reported selected factorisations up to 48 bits using ten superconducting qubits.

The hybrid lattice/QAOA paper estimated that 372 physical qubits and circuit depth in the thousands could challenge RSA-2048.

A simulation study compared QAOA and VQE factoring variants and projected VQF resources with input size.

A six-flux-qubit multiplier unit demonstrated two-bit multiplication or factorisation candidate states, with larger scale-up studied by design and simulation.

A generalized-Grover protocol reported selected composite factorisations, including a trillion-scale target, on three or four IBM qubits.

A counterdiabatic trapped-ion experiment reported improved success on the same classically reduced 48-bit target used in the Yan et al. work.

D-Wave hybrid tooling was reported to factor 102,454,763 and 1,000,070,001,221.

Public statements claimed full factorisation of RSA-2048 using measurement-free quantum methods on inexpensive conventional hardware.

A high-performance classical simulator examined Shor circuits for more than 60,000 scenarios and integers up to 549,755,813,701.

Secondary coverage framed a 22-bit direct annealing result and 50-bit hybrid progress as breaking RSA or military-grade encryption.

A D-Wave paper reported ten specially constructed 2,048-bit semiprimes under a title describing factorisation of an RSA-2048 integer.

A D-Wave Advantage multiplier-QUBO experiment presented 8,219,999 as a hardware factoring record.

A D-Wave paper reported a direct 22-bit QUBO factorisation and a hybrid closest-vector/annealing result described as a first 50-bit RSA-integer factorisation.

Updated fault-tolerant estimates projected RSA-2048 with fewer than one million noisy qubits and less than one week.

A hybrid D-Wave/classical method reported a selected 80-bit factorisation and broader applicability from 4 to 80 bits.

A bibliographic index reports a hybrid D-Wave method extending the prior work to a 90-bit RSA integer.

A direct VQE encoding without arithmetic simplification factored selected numbers through 253 on IBM hardware and reached 1,048,561 only in ideal simulation.

A preprint reported a first experimental demonstration of a simplified Regev factoring circuit for 35 with superconducting-hardware data and lattice postprocessing.

A reconfigurable neutral-atom architecture analysis projected cryptographic-scale Shor computations with as few as about 10,000 physical qubits.

A modular fault-tolerant architecture projected roughly half a million physical qubits for an RSA-2048 workload under specified interconnect and measurement assumptions.

The proposed Pinnacle qLDPC architecture estimated RSA-2048 factoring with fewer than 100,000 physical qubits under stated conditions.

A post gave an O((log n)^2) operation count for factoring on an idealised machine with constant-cost arithmetic on arbitrarily large integers.

A fault-tolerant surface-code estimate projected factoring RSA-2048 in about eight hours with about 20 million noisy physical qubits.

A hybrid annealing formulation reported factoring 1,005,973 with 89 binary variables.

An optimised Ising formulation reported factoring integers through 1,028,171 with 88 logical variables.

A cat-code and multimode-memory architecture estimated RSA-2048 factoring with 13,436 processor qubits in 177 days.

A simulation study compared QAOA and VQE factoring variants and projected VQF resources with input size.

A high-performance classical simulator examined Shor circuits for more than 60,000 scenarios and integers up to 549,755,813,701.

Updated fault-tolerant estimates projected RSA-2048 with fewer than one million noisy qubits and less than one week.

A reconfigurable neutral-atom architecture analysis projected cryptographic-scale Shor computations with as few as about 10,000 physical qubits.

A modular fault-tolerant architecture projected roughly half a million physical qubits for an RSA-2048 workload under specified interconnect and measurement assumptions.

The proposed Pinnacle qLDPC architecture estimated RSA-2048 factoring with fewer than 100,000 physical qubits under stated conditions.

A circuit proposal claimed roughly 3.009 times as many decimal digits could be factored for the same construction-cost-times-latency budget.

A three-qubit NMR experiment encoded and recovered factors of 21 with an adiabatic method, while favourable runtime scaling was studied in simulation.

An ion-trap experiment presented a scalable Kitaev-style Shor architecture and factored 15 with generalized modular multipliers.

An automated D-Wave 2000Q QUBO pipeline reported selected hardware factorisations through 103,459.

A hybrid adiabatic IBM experiment factored 35 after classical reduction of the biprime optimisation problem.

A variational imaginary-time method reported hardware factorisations through 91 and a larger set in simulation.

A six-flux-qubit multiplier unit demonstrated two-bit multiplication or factorisation candidate states, with larger scale-up studied by design and simulation.

A classical tensor-network method reported finite-size numerical evidence of polynomial resource scaling, factoring RSA semiprimes to 100 bits and simulating encodings to 130 bits.

A hybrid D-Wave/classical method reported a selected 80-bit factorisation and broader applicability from 4 to 80 bits.

A preprint conjectured a classical subexponential factorisation method conditional on finding an elliptic curve and point with specified even-order properties.

A direct VQE encoding without arithmetic simplification factored selected numbers through 253 on IBM hardware and reached 1,048,561 only in ideal simulation.

Headline-level retellings collapsed the verified factorisation of the single RSA-129 challenge into the broader claim that RSA had been cracked.

A proposal and newspaper headline claimed a fast RSA decode by finding an exponent x with 2^x=1 mod N, based on small spreadsheet tests.

A deterministic digit-by-digit depth-first search was presented as a fast RSA-factoring algorithm whose runtime depends on decimal input length.

A preprint claimed deterministic polynomial-time factorisation by reducing the problem to two-dimensional convex integer minimisation.

A methodological construction showed that answer-dependent compiled Shor circuits can appear to factor arbitrarily large selected products in constant time with two coherent qubits.

A compiled IBM Shor experiment attempted to factor 35 with base 4.

Reports described 256-bit demonstrations in about 50 seconds, projected 512 bits in about five hours, and promoted the reciprocal method as a practical threat to public-key cryptography.

A worked example for 187=11×17 was presented as logarithmic-time integer factorisation.

The 2021 preprint projected factoring 400- and 800-bit integers with low-dimensional lattices and low operation counts, concluding that the method destroyed RSA.

The hybrid lattice/QAOA paper estimated that 372 physical qubits and circuit depth in the thousands could challenge RSA-2048.

Secondary coverage framed a 22-bit direct annealing result and 50-bit hybrid progress as breaking RSA or military-grade encryption.

A preprint claimed O(log^2 n log log n) deterministic factoring of arbitrary RSA semiprimes by monotone binary search over rounded roots.

A seven-spin liquid-state NMR experiment implemented a compiled Shor instance for 15.

A one-way photonic architecture demonstrated a compiled Shor circuit for 15.

A four-qubit photonic circuit implemented a compiled Shor factorisation of 15.

Four photonic qubits on an integrated silica-on-silicon chip ran a compiled Shor circuit for 15.

A four-qubit NMR system ran an instance-reduced adiabatic Hamiltonian whose ground state encoded 143=11×13.

A three-qubit superconducting processor ran a compiled Shor circuit for 15 and reported correct factors in 48% of repetitions.

A two-photon recycled-qubit circuit was presented as a compiled order-finding method to factor 21.

Simplified Shor circuits were proposed for selected products of Fermat primes, including 51 and 85.

Selected semiprimes including 3,599, 11,663 and 56,153 were reduced to the same four-variable Hamiltonian family used for 143, with a three-variable construction for 175.

A D-Wave 2X experiment reported selected biprime factorisations above 200,000 after Gröbner-basis preprocessing.

A three-qubit room-temperature NMR experiment reported factorisation of 291,311 after classical reduction to a three-variable Hamiltonian.

A hybrid IBM scheme reported factoring 4,088,459 and other selected integers with very small circuits.

A D-Wave 2000Q multiplication-table formulation was demonstrated on selected targets through 376,289 using up to 94 logical variables.

Compiled IBM circuits recovered expected periods for 15 and assigned the correct period for a selected 21 instance.

A four-photon cluster-state circuit using a semiconductor quantum-dot source factored 15.

QAOA-based variational factoring ran selected targets including 1,099,551,473,989 on a superconducting processor using three to five qubits.

A five-qubit compiled quantum-phase-estimation circuit on IBM processors completed factor extraction for 21.

A hybrid Schnorr-lattice/QAOA experiment reported selected factorisations up to 48 bits using ten superconducting qubits.

A generalized-Grover protocol reported selected composite factorisations, including a trillion-scale target, on three or four IBM qubits.

A counterdiabatic trapped-ion experiment reported improved success on the same classically reduced 48-bit target used in the Yan et al. work.

A D-Wave paper reported ten specially constructed 2,048-bit semiprimes under a title describing factorisation of an RSA-2048 integer.

A D-Wave Advantage multiplier-QUBO experiment presented 8,219,999 as a hardware factoring record.

A D-Wave paper reported a direct 22-bit QUBO factorisation and a hybrid closest-vector/annealing result described as a first 50-bit RSA-integer factorisation.

A preprint reported a first experimental demonstration of a simplified Regev factoring circuit for 35 with superconducting-hardware data and lattice postprocessing.

The proposed TWINKLE optoelectronic siever was projected to increase factorable size by 100–200 bits and make 512-bit RSA very vulnerable.

A proposed device was projected to perform the NFS matrix step for RSA-1024 in one day for a few thousand US dollars under an optimistic matrix-size assumption.

The TWIRL VLSI design projected NFS sieving of 512-bit inputs in under ten minutes for about US$10,000 and 1,024-bit inputs in under one year for about US$10 million.

A secondary report presented the special-form factorisation of 2^1039−1 as meaning ordinary RSA-1024 was dead.

A workshop talk claimed average-time polynomial SVP/CVP behaviour could yield polynomial-time integer factoring under geometric-series and short-vector assumptions.

Work-in-progress slides proposed a deterministic general factoring algorithm of roughly exp(c√(log N log log N)) complexity, conditional on a missing step.

A Bayesian-network and linear-programming construction was claimed to give deterministic polynomial-time factoring and to warrant re-evaluating factoring-based cryptography.

A CVP chapter used heuristic prime-number-lattice behaviour as a route to polynomial-time factoring.

A Dagstuhl report claimed polynomial-time SVP/CVP for low-relative-density lattices under reasonable heuristics and applied it to factoring, with examples around 10^14.

Two preprints proposed polynomial-time RSA inversion or equivalent-key attacks when associated sequences have polynomially bounded linear complexity.

D-Wave hybrid tooling was reported to factor 102,454,763 and 1,000,070,001,221.

Public statements claimed full factorisation of RSA-2048 using measurement-free quantum methods on inexpensive conventional hardware.

A viXra preprint and follow-up records claimed very short algorithms would factor RSA-2048 or RSA-617, with another result expressly approximate.

Arnold's Factorization Algorithm was described as polynomial-time with potential cryptographic relevance and illustrated on semiprimes up to 12 decimal digits.

A 2025 talk continued the prime-number-lattice polynomial-time programme and estimated an 800-bit input at lattice dimension 900.

A preprint abstract claimed an explicit deterministic and provably polynomial framework for factoring RSA-type semiprimes.

A follow-up manuscript presented an algebraic-analytic framework connecting deterministic polynomial-time semiprime factorisation with the Riemann hypothesis.

A bibliographic index reports a hybrid D-Wave method extending the prior work to a 90-bit RSA integer.

A forum post claimed that the general factoring problem was solved.

A post gave an O((log n)^2) operation count for factoring on an idealised machine with constant-cost arithmetic on arbitrarily large integers.

Headline-level retellings collapsed the verified factorisation of the single RSA-129 challenge into the broader claim that RSA had been cracked.

The proposed TWINKLE optoelectronic siever was projected to increase factorable size by 100–200 bits and make 512-bit RSA very vulnerable.

A proposal and newspaper headline claimed a fast RSA decode by finding an exponent x with 2^x=1 mod N, based on small spreadsheet tests.

A circuit proposal claimed roughly 3.009 times as many decimal digits could be factored for the same construction-cost-times-latency budget.

A seven-spin liquid-state NMR experiment implemented a compiled Shor instance for 15.

A proposed device was projected to perform the NFS matrix step for RSA-1024 in one day for a few thousand US dollars under an optimistic matrix-size assumption.

The TWIRL VLSI design projected NFS sieving of 512-bit inputs in under ten minutes for about US$10,000 and 1,024-bit inputs in under one year for about US$10 million.

A deterministic digit-by-digit depth-first search was presented as a fast RSA-factoring algorithm whose runtime depends on decimal input length.

A forum post claimed that the general factoring problem was solved.

A secondary report presented the special-form factorisation of 2^1039−1 as meaning ordinary RSA-1024 was dead.

A one-way photonic architecture demonstrated a compiled Shor circuit for 15.

A four-qubit photonic circuit implemented a compiled Shor factorisation of 15.

A three-qubit NMR experiment encoded and recovered factors of 21 with an adiabatic method, while favourable runtime scaling was studied in simulation.

Work-in-progress slides proposed a deterministic general factoring algorithm of roughly exp(c√(log N log log N)) complexity, conditional on a missing step.

A workshop talk claimed average-time polynomial SVP/CVP behaviour could yield polynomial-time integer factoring under geometric-series and short-vector assumptions.

Four photonic qubits on an integrated silica-on-silicon chip ran a compiled Shor circuit for 15.

A four-qubit NMR system ran an instance-reduced adiabatic Hamiltonian whose ground state encoded 143=11×13.

A Bayesian-network and linear-programming construction was claimed to give deterministic polynomial-time factoring and to warrant re-evaluating factoring-based cryptography.

A preprint claimed deterministic polynomial-time factorisation by reducing the problem to two-dimensional convex integer minimisation.

A three-qubit superconducting processor ran a compiled Shor circuit for 15 and reported correct factors in 48% of repetitions.

A two-photon recycled-qubit circuit was presented as a compiled order-finding method to factor 21.

A CVP chapter used heuristic prime-number-lattice behaviour as a route to polynomial-time factoring.

Simplified Shor circuits were proposed for selected products of Fermat primes, including 51 and 85.

A methodological construction showed that answer-dependent compiled Shor circuits can appear to factor arbitrarily large selected products in constant time with two coherent qubits.

Selected semiprimes including 3,599, 11,663 and 56,153 were reduced to the same four-variable Hamiltonian family used for 143, with a three-variable construction for 175.

A Dagstuhl report claimed polynomial-time SVP/CVP for low-relative-density lattices under reasonable heuristics and applied it to factoring, with examples around 10^14.

An ion-trap experiment presented a scalable Kitaev-style Shor architecture and factored 15 with generalized modular multipliers.

A D-Wave 2X experiment reported selected biprime factorisations above 200,000 after Gröbner-basis preprocessing.

A three-qubit room-temperature NMR experiment reported factorisation of 291,311 after classical reduction to a three-variable Hamiltonian.

A hybrid IBM scheme reported factoring 4,088,459 and other selected integers with very small circuits.

A D-Wave 2000Q multiplication-table formulation was demonstrated on selected targets through 376,289 using up to 94 logical variables.

Reports described 256-bit demonstrations in about 50 seconds, projected 512 bits in about five hours, and promoted the reciprocal method as a practical threat to public-key cryptography.

Compiled IBM circuits recovered expected periods for 15 and assigned the correct period for a selected 21 instance.

A compiled IBM Shor experiment attempted to factor 35 with base 4.

A fault-tolerant surface-code estimate projected factoring RSA-2048 in about eight hours with about 20 million noisy physical qubits.

A hybrid annealing formulation reported factoring 1,005,973 with 89 binary variables.

A four-photon cluster-state circuit using a semiconductor quantum-dot source factored 15.

An automated D-Wave 2000Q QUBO pipeline reported selected hardware factorisations through 103,459.

A hybrid adiabatic IBM experiment factored 35 after classical reduction of the biprime optimisation problem.

An optimised Ising formulation reported factoring integers through 1,028,171 with 88 logical variables.

The 2021 preprint projected factoring 400- and 800-bit integers with low-dimensional lattices and low operation counts, concluding that the method destroyed RSA.

A worked example for 187=11×17 was presented as logarithmic-time integer factorisation.

QAOA-based variational factoring ran selected targets including 1,099,551,473,989 on a superconducting processor using three to five qubits.

A variational imaginary-time method reported hardware factorisations through 91 and a larger set in simulation.

A five-qubit compiled quantum-phase-estimation circuit on IBM processors completed factor extraction for 21.

A cat-code and multimode-memory architecture estimated RSA-2048 factoring with 13,436 processor qubits in 177 days.

Two preprints proposed polynomial-time RSA inversion or equivalent-key attacks when associated sequences have polynomially bounded linear complexity.

A hybrid Schnorr-lattice/QAOA experiment reported selected factorisations up to 48 bits using ten superconducting qubits.

The hybrid lattice/QAOA paper estimated that 372 physical qubits and circuit depth in the thousands could challenge RSA-2048.

A simulation study compared QAOA and VQE factoring variants and projected VQF resources with input size.

A six-flux-qubit multiplier unit demonstrated two-bit multiplication or factorisation candidate states, with larger scale-up studied by design and simulation.

A generalized-Grover protocol reported selected composite factorisations, including a trillion-scale target, on three or four IBM qubits.

A counterdiabatic trapped-ion experiment reported improved success on the same classically reduced 48-bit target used in the Yan et al. work.

D-Wave hybrid tooling was reported to factor 102,454,763 and 1,000,070,001,221.

Public statements claimed full factorisation of RSA-2048 using measurement-free quantum methods on inexpensive conventional hardware.

A high-performance classical simulator examined Shor circuits for more than 60,000 scenarios and integers up to 549,755,813,701.

A viXra preprint and follow-up records claimed very short algorithms would factor RSA-2048 or RSA-617, with another result expressly approximate.

A classical tensor-network method reported finite-size numerical evidence of polynomial resource scaling, factoring RSA semiprimes to 100 bits and simulating encodings to 130 bits.

Arnold's Factorization Algorithm was described as polynomial-time with potential cryptographic relevance and illustrated on semiprimes up to 12 decimal digits.

Secondary coverage framed a 22-bit direct annealing result and 50-bit hybrid progress as breaking RSA or military-grade encryption.

A D-Wave paper reported ten specially constructed 2,048-bit semiprimes under a title describing factorisation of an RSA-2048 integer.

A D-Wave Advantage multiplier-QUBO experiment presented 8,219,999 as a hardware factoring record.

A D-Wave paper reported a direct 22-bit QUBO factorisation and a hybrid closest-vector/annealing result described as a first 50-bit RSA-integer factorisation.

A preprint conjectured a classical subexponential factorisation method conditional on finding an elliptic curve and point with specified even-order properties.

A 2025 talk continued the prime-number-lattice polynomial-time programme and estimated an 800-bit input at lattice dimension 900.

A preprint abstract claimed an explicit deterministic and provably polynomial framework for factoring RSA-type semiprimes.

A follow-up manuscript presented an algebraic-analytic framework connecting deterministic polynomial-time semiprime factorisation with the Riemann hypothesis.

Updated fault-tolerant estimates projected RSA-2048 with fewer than one million noisy qubits and less than one week.

A hybrid D-Wave/classical method reported a selected 80-bit factorisation and broader applicability from 4 to 80 bits.

A bibliographic index reports a hybrid D-Wave method extending the prior work to a 90-bit RSA integer.

A direct VQE encoding without arithmetic simplification factored selected numbers through 253 on IBM hardware and reached 1,048,561 only in ideal simulation.

A preprint reported a first experimental demonstration of a simplified Regev factoring circuit for 35 with superconducting-hardware data and lattice postprocessing.

A preprint claimed O(log^2 n log log n) deterministic factoring of arbitrary RSA semiprimes by monotone binary search over rounded roots.

A reconfigurable neutral-atom architecture analysis projected cryptographic-scale Shor computations with as few as about 10,000 physical qubits.

A modular fault-tolerant architecture projected roughly half a million physical qubits for an RSA-2048 workload under specified interconnect and measurement assumptions.

The proposed Pinnacle qLDPC architecture estimated RSA-2048 factoring with fewer than 100,000 physical qubits under stated conditions.